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december 2007 rev 2 1/22 1 M36P0R8070E0 256 mbit (x16, multiple bank, multilevel, burst) flash memory 128 mbit (burst) psram, 1.8 v supply, multichip package features multichip package ? 1 die of 256 mbit (16 mb x 16, multiple bank, multilevel, burst) flash memory ? 1 die of 128 mbit (8 mb x16) psram supply voltage ?v ddf = v ccp = v ddq = 1.7 to 1.95 v ?v ppf = 9 v for fast program (12 v tolerant) electronic signature ? manufacturer code: 20h ? device code: 8818 package ?ecopack? flash memory synchronous/asynchronous read ? synchronous burst read mode: 108 mhz, 66 mhz ? asynchronous page read mode ? random access: 93 ns programming time ? 4 s typical word program time using buffer enhanced factory program command memory organization ? multiple bank memory array: 32 mbit banks ? four efa (extended flash array) blocks of 64 kbits dual operations ? program/erase in one bank while read in others ? no delay between read and write operations security ? 64bit unique device number ? 2112 bit user programmable otp cells 100 000 program/erase cycles per block block locking ? all blocks locked at power-up ? any combination of blocks can be locked with zero latency ?wp f for block lock-down ? absolute write protection with v ppf = v ss cfi (common flash interface) psram access time: 70 ns asynchronous page read ? page size: 4, 8 or 16 words ? subsequent read within page: 20 ns synchronous burst read/write low power consumption ? active current: < 25 ma ? standby current: 200 a ? deep power-down current: 10 a low power features ? pasr (partial array self refresh) ? dpd (deep power-down) mode tfbga107 (zac) fbga www.numonyx.com
contents M36P0R8070E0 2/22 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 address inputs (a0-a23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 data input/output (dq0-dq15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 latch enable (l ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 clock (k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 wait (wait) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 flash chip enable input (e f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7 flash output enable inputs (g f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8 flash write enable (w f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.9 flash write protect (wp f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.10 flash reset (rp f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.11 flash deep power-down (dpd f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.12 psram chip enable input (e p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.13 psram write enable (w p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.14 psram output enable (g p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.15 psram upper byte enable (ub p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.16 psram lower byte enable (lb p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.17 psram configuration register enable (cr p ) . . . . . . . . . . . . . . . . . . . . . 11 2.18 v ddf supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.19 v ccp supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.20 v ddq supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.21 v ppf program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.22 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
M36P0R8070E0 contents 3/22 6 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
list of tables M36P0R8070E0 4/22 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 7. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
M36P0R8070E0 list of figures 5/22 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 figure 5. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. tfbga107 8 x 11 mm 9 x 12 active ball array, 0.8 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
description M36P0R8070E0 6/22 1 description the M36P0R8070E0 combines two memories in a multichip package: 256-mbit multiple bank flash memory (the m58pr256j) 128-mbit psram (the m69kb128aa). this datasheet should be read in conjunction with the m58pr256j and m69kb128aa datasheets, which are available from your local numonyx distributor. recommended operating conditions do not allow more than one memory to be active at the same time. the memory is offered in a stacked tfbga107 package, and it is supplied with all the bits erased (set to ?1?). figure 1. logic diagram ai12097 24 a0-a23 e f dq0-dq15 v ddq M36P0R8070E0 g f v ss 16 w f rp f wp f v ddf dpd f e p g p w p ub p lb p v ppf v ccp l k cr p wait
M36P0R8070E0 description 7/22 table 1. signal names name function a0-a23 (1) 1. a23 is an address input for the flash memory component only. address inputs dq0-dq15 common data input/output v ddq common flash and psram power supply for i/o buffers v ppf flash memory optional supply voltage for fast program and erase v ddf flash memory power supply v ccp psram power supply v ss ground l latch enable input k burst clock wait wait output nc not connected internally du do not use as internally connected flash memory e f chip enable input g f output enable input w f write enable input rp f reset input wp f write protect input dpd f deep power-down psram e p chip enable input g p output enable input w p write enable input cr p configuration register enable input ub p upper byte enable input lb p lower byte enable input
description M36P0R8070E0 8/22 figure 2. tfbga connections (top view through package) ai112006 nc dq14 dq0 a16 wait dq13 dq8 h dq7 d c a17 a22 b a21 a 8 7 6 5 4 3 2 1 a5 a3 g f e a1 du k a7 a2 a8 nc a11 w p a13 du 9 a4 a12 m l k j dq15 v ss nc du nc dq6 nc du dq12 l nc dq4 dq10 v ss v ppf a18 v ss dq11 dq1 a23 nc nc a19 nc du dq9 a14 nc a20 v ddf dq3 dq5 dq2 a6 du du du du nc nc du nc nc nc v ccp dpd f v ss nc v ss nc v ss v ss v ddq v ddq du du du lb p e p a9 wp f a10 a15 ub p rp f w f g p a0 nc e f g f v ccp v ddq cr p v ss v ddq v ddf v ss v ss v ss v ss
M36P0R8070E0 signal descriptions 9/22 2 signal descriptions see figure 1: logic diagram and table 1: signal names for a brief overview of the signals connected to this device. 2.1 address inputs (a0-a23) addresses a0-a22 are common inputs for the flash memory and psram components. address a23 is an input for the flash memory component only. the address inputs select the cells in the flash memory array to access during bus read operations. during bus write operations they control the commands sent to the command interface of the flash memory?s program/erase controller. in the psram the address inputs select the cells in the memory array to access during bus read and write operations. 2.2 data input/output (dq0-dq15) the data i/o output the data stored at the selected address during a bus read operation or input a command or the data to be programmed during a bus write operation. for the psram component, the upper byte data inputs/outputs (dq8-dq15) carry the data to or from the upper part of the selected address when upper byte enable (ub p ) is driven low. the lower byte data inputs/outputs (dq0-dq7) carry the data to or from the lower part of the selected address when lower byte enable (lb p ) is driven low. when both ub p and lb p are disabled, the data inputs/ outputs are high impedance. 2.3 latch enable (l ) the latch enable pin is common to the flash memory and psram components. for more details about the latch enable signal, please refer to the datasheets of the respective memory components: m69kb128aa for the psram and m58pr256j for the flash memory. 2.4 clock (k) the clock input pin is common to the flash memory and psram components. for more details about the clock signal, please refer to the datasheets of the respective memory components: m69kb128aa for the psram and m58pr256j for the flash memory.
signal descriptions M36P0R8070E0 10/22 2.5 wait (wait) wait is an output pin common to the flash memory and psram components. however, the wait signal does not behave in the same way for the psram and the flash memory. for details on this signal, please refer to the m69kb128aa datasheet for the psram and to the m58pr256j datasheet for the flash memory. 2.6 flash chip enable input (e f ) the chip enable input activates the control logic, input buffers, decoders, and sense amplifiers of the flash memory. when chip enable is low, v il , and reset is high, v ih , the device is in active mode. when chip enable is at v ih the flash memory are deselected, the outputs are high impedance and the power consumption is reduced to the standby level. it is not allowed to have e f at v il and e p at v il at the same time. only one memory component can be enabled at a time. 2.7 flash output enable inputs (g f ) the output enable input controls the data outputs during flash memory bus read operations. 2.8 flash write enable (w f ) the write enable input controls the bus write operation of the flash memory command interface. the data and address inputs are latched on the rising edge of chip enable or write enable, whichever occurs first. 2.9 flash write protect (wp f ) write protect is an input that provides additional hardware protection for each block. when write protect is low, v il , lock-down is enabled and the protection status of the locked-down blocks cannot be changed. when write protect is at high, v ih , lock-down is disabled and the locked-down blocks can be locked or unlocked. (see the lock status table in the m58pr256j datasheet). 2.10 flash reset (rp f ) the reset input provides a hardware reset of the flash memories. when reset is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the reset supply current i dd2 . after reset, all blocks are in the locked state and the configuration register is reset. when reset is at v ih , the device is in normal operation. upon exiting reset mode the device enters asynchronous read mode, but a negative transition of chip enable or latch enable is required to ensure valid data outputs. the reset pin can be interfaced with 3 v logic without any additional circuitry, and can be tied to v rph .
M36P0R8070E0 signal descriptions 11/22 2.11 flash deep power-down (dpd f ) the deep power-down input put sthe device in deep power-down mode. when the device is in standby mode and the enhanced configuration register bit ecr15 is set, asserting the deep power-down input causes the memory to enter deep power-down mode. when the device is in the deep power-down mode, the memory cannot be modified and the data is protected. the polarity of the dpd f pin is determined by ecr14. the deep power-down input is active low by default. 2.12 psram chip enable input (e p ) the chip enable input activates the psram when driven low (asserted). when de- asserted (v ih ), the device is disabled, and goes automatically in low-power standby mode or deep power-down mode, according to the rcr (refresh configuration register) setting. 2.13 psram write enable (w p ) write enable, w p , controls the bus write operation of the psram. when asserted (v il ), the device is in write mode and write operations can be performed either to the configuration registers or to the memory array. 2.14 psram output enable (g p ) when held low, v il , the output enable, g p , enables the bus read operations of the psram. 2.15 psram upper byte enable (ub p ) the upper byte enable, ub p , gates the data on the upper byte data inputs/outputs (dq8- dq15) to or from the upper part of the selected address during a write or read operation. 2.16 psram lower byte enable (lb p ) the lower byte enable, lb p , gates the data on the lower byte data inputs/outputs (dq0- dq7) to or from the lower part of the selected address during a write or read operation. if both lb p and ub p are disabled (high), the device disables the data bus from receiving or transmitting data. although the device seems to be deselected, it remains in an active mode as long as e p remains low. 2.17 psram configuration register enable (cr p ) when this signal is driven high, v ih , bus read or write operations access either the value of the rcr or the bcr (bus configuration r egister) according to the value of a19.
signal descriptions M36P0R8070E0 12/22 2.18 v ddf supply voltage v ddf provides the power supply to the internal core of the flash memory. it is the main power supply for all flash memory operations (read, program and erase). 2.19 v ccp supply voltage the v ccp supply voltage is the core supply voltage. 2.20 v ddq supply voltage v ddq provides the power supply for the flash me mory and psram i/o pins. this allows all outputs to be powered independently of the flash memory and psram core power supplies, v ddf and v ccp . 2.21 v ppf program supply voltage v ppf is both a control input and a power supply pin for the flash memory. the two functions are selected by the voltage range applied to the pin. if v ppf is kept in a low voltage range (0v to v ddq ) v ppf is seen as a control input. in this case a voltage lower than v pplk gives absolute protection against program or erase, while v ppf > v pp1 enables these functions. v ppf is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. if v ppf is in the range of v pph it acts as a power supply pin. in this condition v ppf must be stable until the program/erase algorithm is completed. 2.22 v ss ground v ss is the common ground reference for all voltage measurements in the flash memory (core and i/o buffers) and psram chips. it must be connected to the system ground. note: each flash memory device in a sys tem should have its supply voltage (v ddf ) and the program supply voltage v ppf decoupled with a 0.1 f cera mic capacitor close to the pin (high-frequency, inherently-low inductance capacitors should be as close as possible to the package). see figure 5: ac measurement load circuit . the pcb track widths should be sufficient to carry the required v ppf program and erase currents .
M36P0R8070E0 functional description 13/22 3 functional description the psram and flash memory components have separate power supplies but share the same grounds. they are distinguished by two chip enable inputs: e f for the flash memory and e p for the psram. recommended operating conditions do not allow more than one device to be active at a time. the most common example is a simultaneous read operations on the flash memory and the psram which results in a data bus contention. therefore, it is recommended to put the other device in the high impedance state when reading the selected device. figure 3. functional block diagram ai12098 e p cr p g p w p a0-a22 128 mbit psram ub p lb p wait k v ddq v ss v ccp l 256 mbit flash memory e f g f v ddf w f rp f wp f v ppf a23 dq0-dq15 dpd f
functional description M36P0R8070E0 14/22 table 2. main operating modes (1) operation e f g f w f rp f dpd f (2) wait (3) l e p cr p g p w p lb p u b p a18- a19 (4) a0- a17 a20- a22 dq15- dq0 flash memory bus read v il v il v ih v ih de- asserted (5) v il (6) psram must be disabled. only one flash memory can be enabled at a time. flash data out bus write v il v ih v il v ih de- asserted (5) v il (6) flash data in address latch v il xv ih v ih de- asserted (5) v il flash data out or hi-z (7) output disable v il v ih v ih v ih de- asserted (5) hi-z x any psram mode is allowed. flash memories must be disabled. hi-z standby v ih xxv ih de- asserted (5) hi-z x hi-z reset x x x v il de- asserted (5) hi-z x hi-z deep power- down v ih x x v ih asserted (8) hi-z x hi-z psram read flash memories must be disabled low-z v il v il v il v il v ih v il v il valid psram data out write low-z v il v il v il xv il v il v il valid psram data in read configuration register low-z v il v il v ih v il v ih v il v il 00(rcr) 10(bcr) x1(didr) x bcr/rc r/didr contents program configuration register (9) low-z v il v il v ih xv ih xx 00(rcr) 10(bcr) bcr/ rcr data hi-z standby any flash memory mode is allowed. only one flash memory can be enabled at a time hi-z x v ih v il xx x x hi-z deep power- down (10) hi-z x v ih xxxx x hi-z 1. x = don?t care. 2. the dpd f signal polarity depends on the value of the ecr14 bit. 3. wait signal polarity is configured using the set configuration register command. see the m58pr256j datasheet for details. 4. a18 and a19 are used to select the bcr (bus configuration register), rcr (refresh conf iguration register) or didr (device id register). 5. if ecr15 is set to '0', the flash memory device cannot enter the deep power-down mode, even if dpd f is asserted. 6. l can be tied to v ih if the valid address has been previously latched. 7. depends on g f . 8. ecr15 has to be set to ?1? for the flas h memory device to enter deep power-down. 9. bcr and rcr only. 10. bit 4 of the refresh configuration register must be set to ?0?, bit 4 (bcr4) of the bus configuration register must be set t o ?0?, and e has to be maintained high, v ih , during deep power-down mode.
M36P0R8070E0 maximum ratings 15/22 4 maximum ratings stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliabilit y. refer also to the numonyx sure program and other relevant quality documents. table 3. absolute maximum ratings symbol parameter value unit min max t a ambient operating temperature ?30 85 c t bias temperature under bias ?30 85 c t stg storage temperature ?55 125 c v io input or output voltage ?0.2 2.45 v v ddf flash memory supply voltage ?1 3 v v ccp psram supply voltage ?0.2 2.45 v v ddq input/output supply voltage ?0.2 2.45 v v ppf flash memory program voltage ?1 12.6 v i o output short circuit current 100 ma t vpph time for v ppf at v pph 100 hours
dc and ac parameters M36P0R8070E0 16/22 5 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables in this section are derived from tests performed under the measurement conditions summarized in table 4., operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 4. ac measurement i/o waveform table 4. operating and ac measurement conditions parameter flash memory psram unit min max min max v ddf supply voltage 1.7 1.95 ? ? v v ccp supply voltage ? ? 1.7 1.95 v v ddq supply voltage 1.7 1.95 1.7 1.95 v v ppf supply voltage (factory environment) 8.5 9.5 ? ? v v ppf supply voltage (application environment) ?0.4 v ddq +0.4 ? ? v load capacitance (c l )3030pf output circuit resistors (r 1 , r 2 )16.716.7k input rise and fall times 3 1 (1) , (2) 1. referenced to v ss . 2. v ccp = v ddq . ns input pulse voltages 0 to v ddq 0 to v ddq v input and output timing ref. voltages v ddq /2 v ddq /2 v ai06161 v ddq 0v v ddq /2
M36P0R8070E0 dc and ac parameters 17/22 figure 5. ac measurement load circuit 1. v dd means v ddf = v ccp . table 5. capacitance (1) 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0 v ? 12 pf c out output capacitance v out = 0 v ? 15 pf ai06162 v ddq c l c l includes jig capacitance 16.7k device under test 0.1f v dd 0.1f v ddq 16.7k
package mechanical M36P0R8070E0 18/22 6 package mechanical to meet environmental requirements, numonyx offers these devices in ecopack? packages, which have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. figure 6. tfbga107 8 x 11 mm 9 x 12 active ball array, 0.8 mm pitch, package outline 1. drawing is not to scale. e d eb se a2 a1 a tfbga-z2 ddd fd d1 e1 e fe ball "b1"
M36P0R8070E0 package mechanical 19/22 table 6. stacked tfbga107 8 x 11 mm 9 x 12 active ball array, 0.8 mm pitch, package data symbol millimeters inches typ min max typ min max a1.200.047 a1 0.20 0.008 a2 0.85 0.033 b 0.35 0.30 0.40 0.014 0.012 0.016 d 8.00 7.90 8.10 0.315 0.311 0.319 d1 6.40 0.252 ddd 0.10 0.004 e 11.00 10.90 11.10 0.433 0.429 0.437 e1 8.80 0.346 e 0.80 0.031 fd 0.80 0.031 fe 1.10 0.043 se 0.40 0.016
part numbering M36P0R8070E0 20/22 7 part numbering note: devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the numonyx sales office nearest to you. table 7. ordering information scheme example: M36P0R8070E0 zac e device type m36 = multichip package (flash + psram) flash 1 architecture p = multilevel, multiple bank, large buffer flash 2 architecture 0 = no die operating voltage r = v ddf = v ccp = v ddq = 1.7 to 1.95 v flash 1 density 8 = 256 mbits flash 2 density 0 = no die ram 1 density 7 = 128 mbits ram 0 density 0 = no die parameter blocks location e = even block flash memory configuration product version 0 = 90 nm flash technology, 93 ns speed; 0.11 m psram technology, 70 ns speed package zac = stacked tfbga107 c stacked footprint. option e = ecopack package, standard packing f = ecopack package, tape and reel packing
M36P0R8070E0 revision history 21/22 8 revision history table 8. document revision history date revision changes 2-oct-2007 1 initial release. 10-dec-2007 2 applied numonyx branding.
M36P0R8070E0 22/22 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties re lating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 11/5/7, numonyx, b.v., all rights reserved.

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